Design-for-Testability Engineer, OPD Hardware - Bengaluru, India - ADCI - BLR 14 SEZ

    ADCI - BLR 14 SEZ
    ADCI - BLR 14 SEZ Bengaluru, India

    Found in: Talent IN C2 - 1 week ago

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    Full time
    Description

    The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers.

    We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa.

    We want you to help us build on the success of our first generation of ML accelerator at edge.

    Work hard. Have fun. Make history.

    At Amazon, DFT (Design-for-Testability) is a multi-faceted job that involves architecture definition, logic design, verification, test patterns generation, chip bring-up and more.

    As a DFT Engineer, you will impact and see the device through its entire lifecycle, from definition stage to high volume production.

    You will be working in close collaboration with multiple VLSI engineering groups including design, verification, backend, test, reliability and more.


    As part of the chip design group, you will: - Contribute to the design and verification of DFT logic and components

    • Help to drive the signoff on a generation of highquality test and debug patterns for high coverage on silicon
    • Review signoff level timing closure using static timing analysis of DFT modes
    • Perform wafer probe testing, ATE testing, silicon bringup, diagnosis and support for physical failure analysis
    • Take high volume chips to production with high coverage ATE test program
    We are open to hiring candidates to work out of one of the following locations:

    Bangalore, KA, IND

    BASIC QUALIFICATIONS

    • BS degree in Computer Engineering/Electrical Engineering
    • 5+ years in semiconductor companies as a DFT lead
    • Chip design experience in Verilog and System Verilog
    • Chip verification experience, UVM methodology
    • Scan insertion tools and methodologies
    • MBIST and BISR, BIHR insertion tools and methodologies
    • EFUSE controllers and related structures
    • Gatelevel simulations
    • Static timing analysis, DFT related timing closure
    • Scripting (Perl/Tcl)
    PREFERRED QUALIFICATIONS

    • MS or PhD degree in Computer Engineering/Electrical Engineering or related field
    • Excellent communication skills. Should be able to well communicate and establish relations with internal "customers",
    • Manufacturing, and equipment vendors
    • Energetic, selfmotivated
    • Proactive, oriented on execution
    • Attentive to details and quality
    • Team player, with the ability to work in a rapidly evolving/changing environment
    • Ability to work well with overseas partners