- Master's or PhD degree in VLSI/Electronics and Communications Engineering
- Strong understanding of physical design and STA
- Experience of 5-10 years in STA.
Lead STA Engineer - Noida, India - NXP Semiconductors
Description
Job Description
The Digital Physical Design Engineer is responsible for a Timing Convergence (STA).
The individual is responsible from writing timing constraints, interacting with different functions like IP, frontend, DFT, Verification to mature the timing constraints.
Responsible for interactions with backend functions such as synthesis and PNR team for delivering constraints and achieve complete timing closure with minimum iterations, with PDN and PISI teams for the respective deliverables.
The individual contributes to the problem solving and writing automation scripts supporting the common STA framework.
In addition, the candidate should have excellent understanding of synthesis, Clock Tree synthesis and PNR concepts and tools.
The candidate is expected to lead the STA team at block level analysis and top level STA analysis. The candidate is expected to mentor and train the juniors.
Preferred Qualifications:
NXP Introduction:
NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.
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