VLSI - DFT Senior Engineer/Lead Engineer - India - Eteros Technologies

Description

Company: Eteros Technologies India Private Limited

Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad

• Our world-wide customers are amongst The Who's who in the semiconductor industry. Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies.

• Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Eteros engineers work with some of the brightest, innovative and successful engineers and leaders around the world. A one-of-a-kind opportunity where young Eteros engineers showcase their ability and experience world-wide from day 1 while learning from some of the world's most well-respected companies.

• We are not your traditional design services company offering staff augmentation. Eteros engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery, whether it is Implementation, Digital and Mixed Signal Verification, DFT or Analog Design and Layout. Eteros and our engineers work closely with our customers to define and set methodologies and design flows.

• Eteros invests in our engineers. Our engineers are continuously learning, on and off the job. They are able to grow the breadth and depth of knowledge. We believe in preparing our employees for the fast-track in career development as well as longevity

Job Title/Role: DFT - Senior Engineer/Lead

Location: Bangalore/Hyderabad/Ahmedabad

ExperienceLevel : 4+ Years

Industry: Semiconductors

EmploymentType : Full-time

JobFunctions : Engineering

Summary

Join a development team as a DFT Engineer on an advanced mixed signal chip for a high-profile Silicon Valley startup.

In this highly visible role, as part of a highly talented team you will be at the heart of the Soc design effort interfacing with all disciplines with critical impact in getting functional products to of customers quickly. As a DFT Engineer, you will be a part of the SOC digital design team responsible for developing and implementing DFT for the designs.

Responsibilities

• Defect modelling and test methodology development at advanced process nodes

• Perform top/block-level DFT insertion including scan compression, boundary scan, , ATPG and pattern simulation

• DFT – full DFT (stuck-at, transition, etc.), MBIST, JTAG, Boundary SCAN, BIST

• Verify DFT circuitry and interface with other blocks, debug timing simulation issues

• Closely work with physical design team to generate and validate timing constraints

• Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning

• Be able to work independently and own the task from DFT specification to final pattern delivery

Requirements

• BTech/MTech/PhD with in Electrical or Computer engineering

• 4-12years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs

• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST

• Experience with Cadence & Synopsys DFT tools is required.

• Strong programming skills in Perl/TCL/C++ and shell scripting is required

• Must be able to solve complex problems and independently drive tasks to completion in a timely manner.

• Be able to work under limited supervision and take complete accountability.

• Excellent written and verbal communication skills

What's in it for you

• Work on leading edge technologies

• An opportunity for career development and growth

• Competitive compensation

• Medical Benefits and more