Memory Layout Engineer - Bengaluru, India - Hiringlabs Business Solutions

Description

Responsible for MemoryCompiler layout development andverification. Responsible for Layout design and development of Memory blocks suchas Array Row/ Column decoder sense amplifier precharge Controlblocks for SRAM. Perform layout verification like LVS/ DRC/ Latchup quality checkand documentation. Responsible for ontime delivery of blocklevel layouts withacceptable quality.
lvs,layout design and development of memoryblocks,drc,quality check,lvs/ drc/ latchup verification,memorylayout,lacthup,memory compiler layoutdevelopment,documentation