Principal STA/Synthesis Engineer - Hyderabad

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. · ...

At AMD our mission is to build great products that accelerate next-generation computing experiences from AI and data centers to PCs gaming and embedded systems. · Bachelors with 2 years of experience or Masters degree with 1 year of experience in Electrical Engineering · Responsi ...

The role involves planning and executing front end implementation of IPs and its closure. This includes ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. · Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayo ...

The focus of this role is to plan and execute the front end implementation of IPs and its closure. · ...

Join AMD as Synthesis STA Engineer. · Plan and execute front end implementation of IPs. · ...

We are seeking a talented Implementation Engineer to join our dynamic team. · This is what you are responsible for : · - Synthesis and STA (static timing analysis).- Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL.- Pr ...

At AMD our mission is to build great products that accelerate next-generation computing experiences from AI and data centers to PCs gaming and embedded systems Grounded in a culture of innovation and collaboration we believe real progress comes from bold ideas human ingenuity and ...

+ WHAT YOU DO AT AMD CHANGES EVERYTHING+ · At AMD our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers to PCs gaming and embedded systems. · + Grounded in a culture of innovation and collaboration we believe real pr ...

We are seeking an experienced Senior/Lead STA/Synthesis Engineer to join our team in Hyderabad. In this role you will be responsible for block/chip tile synthesis to achieve the best PPA and constraint generation and maintenance for block/soc for complex hierarchical designs. · - ...

+Job summary · Renesas is seeking a Staff/Senior Staff Engineer with expertise in Logic Synthesis and Static Timing Analysis (STA). The role involves driving RTL-to-gate-level implementation, · +ResponsibilitiesPerform logic synthesis for large-scale ASIC designs using Synopsys D ...

*Company Description* · Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infr ...

+We are looking for a Staff/Senior Staff Engineer with deep expertise in Logic Synthesis and/or Static Timing Analysis (STA). This role involves driving RTL-to-gate-level implementation, · +Perform logic synthesis for large-scale ASIC designs using Synopsys Design Compiler and Ca ...

THE ROLE: · The focus of this role is to execute the front end implementation of sub-blocks or IP. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. · KEY RESPONSIBILITIES: · Responsible fo ...

We are looking for a Staff/Senior Staff Engineer with deep expertise in Logic Synthesis and/or Static Timing Analysis (STA). · This role involves driving RTL-to-gate-level implementation, · timing closure, · and optimization for complex SoCs across advanced technology nodes.8-14 ...

Job Requirements · Job Title: STA / Synthesis - Technical Manager · Job Type: Full-Time · We are looking for a skilled STA / Synthesis - Technical Manager to join our team at a Product based company. As the Technical Manager, you will be responsible for overseeing the Static ...

A detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints is required. · ...

This job involves timing analysis and timing closure flow development and support with focus on Synopsys Primetime Prime Power Prime Closure Tools. · ...

Synthesis engineer with experience in Genus/FusionCompiler and 22FDX. Bonus for Python/TCL skills. · ...

STA Engineer role involves characterizing STD cells, static timing analysis, writing ARC files, circuit understanding block-wise, full chip level static timing analysis of DRAM. · ...

Principal Engineer responsible for PNR implementation and signoff knowledge in latest nodes. · Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route) · ...