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- You are responsible for Design & Validation of the PDN for full chip which consists of several physical blocks with different power & performance requirements
- Perform Static, Dynamic , Electromigration analysis and provide guidance to implementation team
- Sign off ESD checks (Bumps , Clamps etc.) at full chip level, Work with ESD signoff team
- Deliver the CPM models for AC analysis to SI team for power transition analysis
- Work with implementation team on integration of Analog IPs, It requires Redhawk Pathfinder based resistance checks
- Interface with SI/Pkg team to understand the requirements like ODCs, Routing Resistances & Bump placements.
- Give Feedback to Pkg team on Package parasitic based in DvD Analysis
- Lead the complete PDN signoff activities & guide the PnR engineer for required PG & IR fixes.
- Must have hands on experience with IR drop/droop, in-rush-current/powerup analysis and Electromigration analysis
- Good knowledge on Package design & SI analysis
- Education: completed university degree ( in electronics and communication, electrical engineering or a comparable subject
- Personality and working practice: communicative, problem-solving mindset, responsible, initiative, flexible and target oriented. Comfortable in working in a fast paced, dynamic environment with changing priorities.
- Experience and Knowledge: Expert knowledge of Redhawk tool. Experience with DvD analysis flows like Vector-less, VCD based, Mixed mode
- Qualifications: ability to identify and analyse tasks efficiently within the scope of your work and to develop pragmatic application-specific solutions; pronounced ability to communicate, relevant experience in the methodology of problem solving as well as in the cooperation and leadership of international and cross-functional teams
- Technical Skills: Redhawk, Innovus, ICC2, Perl/Python, Shell Scripting. Languages: fluent in English
Principal engineer, ASIC development engineering - Bengaluru, India - Western Digital
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