Synthesis Lead - Bengaluru - ACL Digital

Location: Bengaluru, India Experience: 10–15 years Industry: Semiconductors | AI | Networking | ASIC Design · Role Overview · As the Synthesis & LEC Lead , you will be the bridge between high-level RTL · architecture and physical reality. In the world of high-performance AI SOCs, ...

The Role The focus of this role will involve driving the physical design flow from timing through final sign-off collaborating closely with cross-functional teams to meet stringent power performance and area (PPA) targets on SerDes PHY IPs. · ...

Work with multiple SOC Design teams to rollout robust Logic Synthesis flows. · ...

We're looking for an experienced NPU Synthesis Lead to drive RTL→Synthesis→Timing closure for NPU IP/subsystems in advanced SoCs. · Lead pre‑/post‑layout timing closure across corners; partner with STA to resolve setup/hold,valid_job":1} } } ...

Work with multiple SOC Design teams to rollout robust Logic Synthesis, UPF synthesis, QoR optimization and netlist Signoff flows · * Provide implementation flows support and issue debugging services · to SOC design teams across various site · * Develop and maintain 3rd party to ...

We're looking for an experienced NPU Synthesis Lead to drive RTL→Synthesis→Timing closure for NPU IP/subsystems in advanced SoCs. · Mandatory Skills (Must‑Have) · 15+ years in ASIC synthesis & timing closure; 3+ years with NPU/AI/DSP cores · ...

The NPU Synthesis Lead will drive synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. · Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. · OR Master's degree in Computer Sci ...

The NPU Synthesis Lead will drive synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. · Synthesis Ownership:Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler,Cadence ...

The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP. · Synthesis Ownership · Lead RTL-to-gate-level synthesis for NPU IP using industry-standard tools. · ...

The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. · ...

The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs.This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architectu ...

The NPU Synthesis Lead will drive synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. · Key Responsibilities include leading synthesis flows, optimizing for PPA (Performance, Power, Area), collaborating with architecture RTL physi ...

We are looking for a skilled STA / Synthesis - Technical Manager to join our team at a Product based company. · As the Technical Manager, you will be responsible for overseeing the Static Timing Analysis (STA) and Synthesis processes to ensure the successful delivery of high-qual ...

Role: STA lead  · Location: Bangalore. · Experience: 5+ Y · Company Name: HCL · Notice Period : Immediate to 30 Days · Below is the JD for STA Lead 5+yrs. · STA / Synthesis (Design Implementation) Lead LD: · ●     Hand-on Experience and Comprehensive knowledge of Synthesis and St ...

We are Hiring | Physical Design – Synthesis Engineer | 4+ Years | Bangalore and Hyderabad. · ...

We are looking for a skilled STA / Synthesis - Technical Manager to join our team at a Product based company. · As the Technical Manager, you will be responsible for overseeing the Static Timing Analysis (STA) and Synthesis processes to ensure the successful delivery of high-qual ...

Strong handson experience with EDA tools like Cadence Innovus Synopsys ICC2 or Mentor Olympus Deep understanding of physical design flow Primetime Experience in hierarchical design multi voltage domains and timing closure Proficiency in scripting Tcl Perl Python for automation an ...

The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. · This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with archite ...

Lead synthesis and formal verification team supporting multiple concurrent chip programs Own synthesis deliverable quality and schedule commitments for all projects Establish synthesis and formal verification methodology standards and guidelines Manage team composition hiring and ...

The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs. · Synthesis Ownership: Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys D ...