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    RTL Principal Design Engineer - Noida, India - Cadence Design Systems

    Cadence Design Systems
    Cadence Design Systems Noida, India

    1 week ago

    Default job background
    Engineering / Architecture
    Description

    1. Proficient in Verilog coding and RTL design, data path designs,

    2. Knowledge of RTL checks ex- LINT, SDC, CDC

    3. Familiar with synthesis flow and timing constraints

    4. Experience in writing Verilog testbench and running simulations.

    5. Desired Protocols knowledge – USB, PCIe, MIPI(DPHY), HDMI/Display

    Nature of work:

    The Candidate will be responsible for the design and implementation of high-speed SerDes PHY at the cutting edge nodes.

    Responsibilities include the architecture of high-speed SerDes IP, design, lint, synthesis, static timing analysis, DFT, formal verification, at block, core, and chip levels.

    Work closely with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits

    Requirement:

    the Candidate is expected to have a good understanding of the digital design flow.

    Proficient in Verilog coding

    • Proficient in high-speed design, RTL coding, datapath designs, working at GHz frequencies.
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