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    RTL Lead - Bengaluru, India - Tech Mahindra

    Tech Mahindra
    Tech Mahindra Bengaluru, India

    6 days ago

    tech mahindra background
    Description
    Hi Folks

    Greetings from Tech MahindraRole:
    RTL Lead EngineerExp: 8+ yearsLocation: Bangalore/ Kochi/ Vizag/ Ahemdabad


    About JobArchitecture DevelopmentExperience in developing High Level Architecture for a Design Requirement from Specification levelExtract Micro Architecture from High Level Architecture specificationRTL Design - Coding & IntegrationDevelop the logic design and Implement register transfer level (RTL) coding for an IP / SoC designOptimize logic to qualify the design to meet power / performance / area / timing goals and ensure Design IntegrityBuild unit level tests to verify the initial design –Ensure designs are delivered on time and with the highest quality by using proper checksProvide Hand-off to Subsystem / SoC Owners for IP IntegrationIntegrate logic of IP blocks and subsystems into a full chip SoC or discrete component designWork with different IP providers to integrate and validate IPs at the Subsystem or SoC levelReview verification plan and implementation to ensure design features are verified correctlyWork closely with Verification team on Feature Extraction, Test Plan Review & sign-off closuresResolve and implement corrective measures for failing RTL tests to ensure correctness of featuresRTL Quality ChecksPerform quality checks on various logic design aspects ranging from RTL to timing/power convergence.

    Hands on experience in running Synopsys Fusion Compiler for Synthesis and Area and performance estimationPerform RTL Lint check, Equivalence checking, CDC checking and support Static Timing Analysis, Static Power Checks,Work closely with different Product owners (Design team / Tool Team / Vendors etc., ) to resolve Design (or)

    Flow issuesTriage all violations for a given Quality check - Accurately Identify & Root Cause issues in design and provide solutionsOwn the RTL QC task for a given IP / Subsystem / SoC – Ensure periodic checks & Clean up issues with new RTL Drops iterativelyEDA Tool Exposure :
    VCS Compile, SG Lint, SG CDC, Synthesis DC / FC CompilerVC LP, Conformal LEC, SAGE Coverage, Calibre, FishtailIntegration Tools - Collage / DeFactoScripting & Automation ExposureKnowledge / Working Experience on Perl, Tcl, Shell scripting is an added advantageKnowledge / Working Experience on debugging Tool Flows & Setup related issues is an added advantage


    Protocol Knowledge (IPs / Processors / IO Bus Protocols etc., )Ability to Understand complex SOC architecture concepts through work experienceProtocol Knowledge – PCIe, CXL, USB, Ethernet, DDR, HBM MIPI, RISC etc.

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