Rtl Design - Bengaluru, India - Adosis

Adosis
Adosis
Verified Company
Bengaluru, India

1 week ago

Deepika Kaur

Posted by:

Deepika Kaur

beBee Recuiter
Description
JD for FPGA/ ASIC Design lead Position


POSITION:

ASIC/FPGA RTL Design Lead:

LOCATION:
Bangalore


QUALIFICATIONS:
BE/B.Tech/ME/M.Tech


EXPERIENCE:
4-10 years


JOB DESCRIPTION:

Key Requirement:

  • RTL designer (using Verilog or SystemVerilog) and good exposure to front-end design tools and flows.
  • Good Knowledge in design of state machines, Datapath's, arbitration and clock domain crossing logic.
  • Good experience in ARM technologies and Integration of various subsystem blocks.
  • Good experience in Low Power Design (UPF) design methodologies.
  • Good experience in Synthesis, Constraint Development, Linting, CDC LEC and STA.

Optional:

  • Experience in scripting like Shell, Perl, Python and PHP
  • Knowledge of low-speed bus protocols (like SPI/QSPI, I2C, I2S & etc) and high-speed serial protocols (PCIe/USB/Ethernet) will be plus.
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