Jyothsna Kamireddy

Seeking a career as a Physical  Designer with an opportunity to work in various technologies to achieve least parasitics with optimized area in an IC while contributing to the symbolic growth of the organization.

As a Placement and Routing (Physical Design) expert with skilled training, I have gained proficiency in working with Synopsys Tools and block-level 40nm technology nodes. My expertise includes a strong understanding of Physical Design flow stages like Floor planning, Power Planning, place and Route,
CTS, Static Timing Analysis, Block level Timing Closure, Resolving various Block level PNR issues, and IR Analysis.

Furthermore, I possess a keen knowledge of Signal Integrity (SI) issues like Crosstalk, Reliability issues like EM, and Antenna Effect. I have extensive experience in Static Timing Analysis (STA),
including fixing setup and hold violations, identifying timing exceptions, timing closure, and assessing the effects of clock skew on timing and timing analysis of latches.

Additionally, I am proficient in Unix/Linux Environment and TCL Scripting, which helps me automate various processes and tasks, increasing productivity and efficiency.

I have done B Tech in the field of Electrical and Electronics from Vignan's Institute of Information and Technology