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Neha Tabassum

Neha Tabassum

ASIC Design Verification Engineer
Hyderabad, Hyderabad


About Neha Tabassum:

I have 5+ years of experience as a verification engineer.

I have always been hard-working, dedicated, top-of-class person.

I passion for my work always reflects in the results in the contributions i have provided to my company.


Professional Skills :

• Hands on experience in front-end functional verification.

• Hands on experience on Block Level Verification closure using UVM methodology. 

• Hands on experience on IP Level verification using mixed methodology environment. 

• Experience in usage of simulation tools/debug environments like Synopsys VCS, Verdi tools, Questa, Visualizer, Manifest flow, Perforce, Methodics, Jenkins. 

• Knowledge on different protocols like AXI,AHB,APB. 

• Knowledge on PERL,TCL Scripting. 

• Knowledge on Verilog, System Verilog, UVM, C++ . 

• Provides status re ports to soc, design, verification teams. 

• Mentored interns in UVM methodology and tools. 

Experience :

Senior Silicon Design Engineer
Silicon Labs Hyderabad
October 2021 – Present ½ Hyderabad,India
Silicon Design Engineer II
AMD Hyderabad
September 2017 - September 2021


Role: Subsystems and Chip level Verification 
• Worked on bring-up of the modules, subsystems, top chip level in new SDE flow for new project.
• Worked on MVP module, HMAC module modifications at chip level and SBC codec at module level. Ran sanity tests and filed  Jiras on rtl design.
• Developed test plans,tests for security protocols - aes, sha3
• Worked on bring-up of tests for host sub-system for various projects.

ACP Variants: ACP5,ACP6.0,ACP6.1,ACP6.2,ACP6.3,ACP7
Role: IP and Block Level Verification for various variants 

Methodology: UVM at Block Level
Worked in verification team as block owner for the below 

ACP to Systemhub (Axi4 to Axi3) : The interface is used by ACP to access system memory.
DirectSRAM (Axi4 to Axi3) : The DirectSram interface is used by host to access ACP memories.
• SRAM Arbiter module : This module deals with the arbitration between four masters writes/reads to 20 memory banks of SRAM.
• Worked on bring-up of complete block level verification test bench environment in UVM using Synopsys VIP.
• Created direct, random and constraint-based block level verification environment.
• Added tests covering different scenarios, added Code and Functional coverage. Worked on the coverage closure.
• Worked closely with designers on ensuring the functionality and corner case scenarios.

Methodology: C++ (IP Level)
Worked in verification team as IP owner for following blocks and on its coverage closure.
Clocks and Resets -IP Level
• Worked on verification of clock functionalities like clock gating, fusing, resets.
• Added direct block level tests, multi-master tests and assertions to check different block’s clock signals functionality, reset functionalities like soft and hard resets, register functionality.

Interrupts - IP Level
• Responsible for Interrupt signals verification at IP level. Added tests to check the interrupt routing to DSPs, external units from all blocks. Worked on code coverage closure.
SHA - IP Level
• Worked on the SHA verification at IP level. Added few tests to improve coverage. Added tests with regard to new DSP introduced.
Doorbell - IP Level
• The interface is used to offoad some tasks from ACP to graphics block. Added functionality tests and closed coverage.



Master of Engineering Embedded Systems and VLSI
Osmania University, Hyderabad, India
June 2016 – May 2018
• CGPA - 9.34
Bachelors of Technology Electronics & Communications Engineering
G.Narayanamma Institute of Technology and Sciences, Hyderabad, India
June 2011 – May 2015
• CGPA - 8.7


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