pushpalathavijendra pushpalatha

Hi 

  I am Pushpalatha , having 11.5 years of work experience as ASIC Verification Engineer. I work on UVM methodology using System Verilog, I have worked in Module based and IP Level Verification. I am a good at solving issues very quickly. 

• Working on USB  IP Verification.
• Used UVM based SV environment to achieve verification goals
• Responsibilities included coding new test cases as per attribute definitions, that is the CTS Requirements for Different Layers in the USB, identifying bugs in reference model and environment and getting them resolved.
• Tools and languages: VCS, UVM, System Verilog

 Worked on GLS + RTL verification For SDC Block.

• Used UVM based SV environment to achieve verification goals
• Responsibilities included coding new test cases as per attribute definitions, identifying bugs in reference model and environment and getting them resolved, debugging regression failures etc.
• Written Assertions, Involved in Toggle Coverage Analysis. 
• Beat deadlines consistently 
• Found around 40 bugs
• Responsible in mentoring and assisting a team of 3.
• Worked on Power Aware GLS.
• Tools and languages: VCS, UVM, System Verilog

Responsible in Testcase Debug and getting them resolved

• Working on USB  IP Verification.
• Used UVM based SV environment to achieve verification goals
• Responsibilities included coding new test cases as per attribute definitions, that is the CTS Requirements for Different Layers in the USB, identifying bugs in reference model and environment and getting them resolved.
• Tools and languages: VCS, UVM, System Verilog