Sevya Multimedia Jobs in India

We are seeking an Analog IP Modeling Engineer specializing in SystemVerilog Real Number Modeling (RNM). In this role, you will bridge the gap between analog design and digital verification by creating high-speed, accurate behavioral models for complex analog IPs. · Develop, verif ...

we are looking for an asic physical design lead with extensive experience in timing closure and full-chip physical design. · ...

Design Verification Engineer · We require experienced engineers with expertise in verifying IPs/full-chips using System Verilog/UVM. · The ideal candidate has at least three years of industry experience in design verification using these technologies. · An understanding of digita ...

We need experienced engineers to verify an IP/full-chip using System Verilog/UVM. Expertise in PCIe/DDR verification is preferable at IP/chip level. · Skills: · Overall 3+ years industry experience in Design Verification using System-Verilog/C/UVM. · Generic knowhow on Dig ...

We need experienced engineers to verify an IP/full-chip using System Verilog/UVM. · ...

We are looking for an ASIC Physical Design Lead with extensive experience in timing closure and full-chip physical design. · The candidate should be adept at interacting with the packaging team and managing tasks such as pads log, bump placement, and RDL routing. · Bachelor's or ...

ASIC Physical Design Lead · Lead complex ASIC projects from Netlist to GDSII with expertise in timing closure and full-chip physical design. · Perform synthesis, place and route, static timing analysis tasks · Collaborate with packaging team on pad log management, bump placement, ...

As ASIC Physical Design Lead y ou will be leading the design of IP/SoC in advanced process technologies, serving global Semiconductor product MNC clients. · Job Summary: · We are looking for an ASIC Physical Design Lead with extensive experience in timing closure and full-c ...

Design Verification Engineer · Verify an IP/full-chip using System Verilog/UVM. · 3+ years experience in Design Verification using System-Verilog/C/UVM. · Digital Design and Verification methodologies. · ...

We are seeking an Analog IP Modeling Engineer specializing in SystemVerilog Real Number Modeling (RNM). In this role, you will bridge the gap between analog design and digital verification by creating high-speed, accurate behavioral models for complex analog IPs. · Model Developm ...

Sevya is architecting and designing a HBM3 transceiver in an advanced FinFET node. · Sevya needs analog designers at all levels with skills in the areas of analog circuit design, custom digital design for SerDes and other high speed IP applications, signal and power integrity mod ...