- Lead and coordinate a team of 5 engineers in mixedsignal, RF, analog and digital domain
- Design and guide projects on advanced mixedsignal circuits data converters, subsampling phase locked loops, serdes and RF circuits in CMOS and BiCMOS and lowpower & lowvoltage applications.
- Skilled in Cadence custom IC EDA tools.
- Achieve successful realization of the layout in close collaboration with layout team.
- Work with application developers to codevelop hardware and software systems.
- Collaborate with teams in India and abroad during project implementation phase.
- PhD/Master degrees from top universities
- Must have a Proven track record of taking multiple mixedsignal ICs through the entire development cycle, from concept to production.
- Successful realization of more than 5 ASIC designs
- In depth knowledge of Cadence custom IC EDA tools
- Proficiency in system and behavioural modeling using MATLAB, System Verilog, Verilog-A/AMS.
- Experience with HDL languages Verilog and/or VHDL is desired.
- Scripting skills: Python, Perl and C is a plus.
- Experience with design, implementation, and development environments for reconfigurable systems (such as FPGAs) is a plus.
- Experience with the silicon manufacturers and working with various CMOS process technologies is a plus.
- Ability to work and manage high performance team.
- One who is individual contributor to the success of the team.
- Ability to adapt to a diverse customer base and willingness to undertake periodic local.
- Travel to customer sites
- Aptitude for learning new technologies and applications
- Good writing, verbal and interpersonal communication skills
- Competent in developing solutions as well as identifying problems
- Knowledge of production processes to ensure quality and robustness
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Lead - Mixed Signal/ASIC Design - Pune, India - ACZ Global Pvt Ltd
Description
Lead of Mixed Signal ASIC DesignJob Description :
Requirements :
Desired Aptitudes :