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    Mixed Signal ASIC Design Lead - Pune, India - ACZ Global Private Limited

    ACZ Global Private Limited
    ACZ Global Private Limited Pune, India

    1 week ago

    Default job background
    permanent Technology / Internet
    Description
    Experience : 10 years + relevant industry experience

    Role :
    Lead of Mixed Signal ASIC Design


    Job Description :

    • Lead and coordinate a team of 5 engineers in mixedsignal, RF, analog and digital domain
    • Design and guide projects on advanced mixedsignal circuits data converters, subsampling phase locked loops, serdes and RF circuits in CMOS and BiCMOS and lowpower & lowvoltage applications.
    • Skilled in Cadence custom IC EDA tools.
    Knowledge of Keysight Pathway desired.

    • Achieve successful realization of the layout in close collaboration with layout team.
    • Work with application developers to codevelop hardware and software systems.
    • Collaborate with teams in India and abroad during project implementation phase.

    Requirements :

    • PhD/Master degrees from top universities
    • Must have a Proven track record of taking multiple mixedsignal ICs through the entire development cycle, from concept to production.
    - + 10 years' experience industrial experience in analog and mixed-signal design.

    • Successful realization of more than 5 ASIC designs
    • In depth knowledge of Cadence custom IC EDA tools
    • Proficiency in system and behavioural modeling using MATLAB, System Verilog, Verilog-A/AMS.
    • Experience with HDL languages Verilog and/or VHDL is desired.
    • Scripting skills like Python, Perl and C is a plus.
    • Experience with design, implementation, and development environments for reconfigurable systems (such as FPGAs) is a plus.
    • Experience with the silicon manufacturers and working with various CMOS process technologies is a plus.
    )
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