- Fullchip DFT leadership experience with multiple design Tape Outs
- Create test architecture and test plans for complex ASICs and drive the Complete Chip DFT implementation & verification tasks
- Proven working experience in Stuck-At, Compression, ATPG, MBIST, BSCAN/JTAG schemes implementation & verifications.
- Should have handled full chiplevel & hierarchical Scan insertion with Compression Techniques (EDT/OPMISR+).
- Hands on Experience with industry standard DFT tools & flows
- Good Knowledge of cross functional domains (SYN, LEC, STA, PD) understanding with owner ship of constraints developments and LEC.
- Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process
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Lead Engineer - Bangalore/Hyderabad/Chennai, India - CHIPSOL PRIVATE LIMITED
Description
Job Description :
DFT Lead/Managerial experience of 7+ years.