- 7+ years of experience in STA.
- Well-versed with the timing closure (STA), timing closure methodologies.
- Pre/Post-layout constraint development to timing closure.
- Handshake with the design team and develop functional/DFT constraints.
- IP level constraint integration.
- Multi-voltage/Switching aware corner definitions.
- RC/C model selection understanding.
- Abstraction expertise like Hyperscale/ILM/ETM.
- RC Balancing and scaling analysis of full chip clock.
- RC Balancing and scaling analysis of critical data paths.
- Good automation skills in PERL, TCL and EDA tool-specific scripting.
- DMSA @ full chip and custom scripts for timing fixes.
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STA LEAD Engineers - Bangalore Urban, India - Mirafra Technologies
Description
Mirafra Technologies Hiring STA Lead Engineers
Experience: years
Notice period - 0 to 30 days
Location - Bangalore
Skills: STA, Prime Time, Timing CLosure
JD:
Please let me know if you will be interested or has any reference for the excellent Job opportunity. We can have a Quick discussion on same.
Thanks and Regards
Sayantika Majumdar
Senior Talent Acquisition Specialist – HWE
Mirafra Technologies
Cell - +91 –
Email –