Associate Ii - Hyderabad, India - UST

UST

Verified Company

Hyderabad, India

1 week ago

Posted by:

Deepika Kaur

beBee Recuiter

Description

Role Proficiency:
Execute any internal project or small tasks of customer project in any field of VLSI Frontend Backend or Analog design under mínimal supervison from the Lead

Outcomes:

As an Individual contributor work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
Analyse and complete the assigned task in the defined domain(s) successfully ontime with mínimal support from senior engineers

Ensure quality delivery as approved by the senior engineer or project lead

Measures of

Outcomes:

Quality verified using relevant metrics by Lead/Manager
Timely delivery verified using relevant metrics by Lead/Manager
Reduction in cycle time and cost using innovative approaches

Number of trainings attended

Outputs Expected:

Quality of the deliverables:

Clean delivery of the module interms of ease in integration at the top level
Ensure functional spec / design guidelines are met 100% of the time without deviation or limitation
Documentation of the tasks and work performed

Timely delivery:

Meet project timelines as given by the team lead/program manager
Help with intermediate tasks delivery by other team members to ensure progress

Teamwork:

Teamwork participation; supporting team members in the time of need
Able to perform additional tasks in case of any team member(s) is not available

Innovation & Creativity:

Proactively plan approach towards repeated work by automating tasks to save design cycle time
Participation in technical discussion

training
forum

Skill Examples:

Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one)
EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one)
Technical Knowledge: (any one)a. Understands IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Knows Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Good knowledge of Physical Design / Circuit Design / Analog Layout d. Good understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Knowledge in Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design
Technology: CMOS FinFet FDSOI 28nm / 22nm / 16ff / 10nm and below
Required technical skills and prior design knowledge to execute assigned tasks
Ability to learn new skills in case required technical skills are not present to a level needed to execute the project
Able to deliver tasks with quality and 100% ontime per quality guidelines and GANTT
Strong communication skills

Good analytical reasoning and problem-solving skills with attention to detail

Knowledge Examples:

Previous project experience in any of the design by executing any one of the following RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.
Good Understanding of the design flow and methodologies used in designing

Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager per skill setAdditional Comments:
DFT resource