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    Design Manager Front End Design and Integration - Bengaluru, India - L&T Semiconductor Technologies

    L&T Semiconductor Technologies
    L&T Semiconductor Technologies Bengaluru, India

    4 days ago

    Default job background
    Engineering / Architecture
    Description

    Role - Design Manager: Front-End Design and Integration

    Stream - R&D

    Reporting To - Chief Development Officer / Global Head of Engineering

    Location -Bengaluru

    Company Overview:

    L&T Semiconductor (LTSCT), a fully owned subsidiary of L&T is the first Indian Semiconductor product company - a fabless company designing & delivering Smart Devices for Global Customers. A company that provides Semiconductor Devices and Technology partnership by helping customers realize energy efficient, high-performance systems to benefit from data, electrification and software defined technology trends.

    Our aim is to build an India-based semiconductor portfolio of Smart Devices across MEMS Sensors, Power, Analog Mixed Signal & RF products, to support Automotive, Industrial, Energy and Telecommunication verticals.

    We have a presence four prominent geographies US, Europe, Japan and India, with offices in Austin, Munich, London, Tokyo, Bangalore and Chennai.

    Our Mission:

    Enabling our customers with a new generation of smart, efficient and market leading power, sense and control Integrated Circuits. Together, creating smart applications and driving decarbonization and digitalization.

    Purpose:

    LTSCT's Chief Development Organization and Global Engineering team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for LTSCT's Automotive, Industrial, Energy and Telecom infra business lines. The team is challenged to produce industry leading solutions covering very cost sensitive, low power devices to highly integrated, high performance, multidomain devices compliant with the latest automotive and industrial safety and security standards.

    Areas Of Responsibility:

    • Work with cross-functional teams to develop scalable SoC design and integration solutions across a wide-range of product types and tiers
    • Define, design and integrate optimal SoC Infrastructure solutions for SoC and its sub-systems
    • Work closely with adjacent SoC functional and Software teams to ensure SoC Infrastructure solutions conform to their needs across all product types
    • Collaborate with Digital and Mixed-Signal IP, Design for Test and Quality teams throughout the entire product development cycle to ensure solution is successfully deployed in commercial product
    • Constantly drive SoC Design and Integration efficiency improvements by closely collaborating with global Design Enablement and Design Automation teams
    • Obtain profound understanding of current ways of working and identify opportunities for SoC execution cycles optimization

    Experience and Qualification:

    • Experience in designing or architecting complex SoCs in leading-edge process nodes with multiple independent compute environments
    • Ability to work at the system-level, identifying optimal partitioning of solutions between hardware and software, working closely with various software teams
    • Experience in defining Foundation IP components to support automation flows
    • High motivation and results orientation
    • Strong problem solving capabilities
    • Excellent interpersonal skills, including written and verbal communication
    • Great teamwork, and presentation abilities
    • Self-driven with good leadership skills
    • Willing and able to mentor junior engineers across multiple design centres

    Qualifiers for the Role / Necessary Experience and Skills Required for the Role:

    • BS/MS/PhD with 10+ years of experience in Semiconductor industry.
    • Experience with System Verilog and front-end tooling (simulation, waveform viewers, lint, CDC, RDC, etc.) is required, as well as highly efficient FE methodologies.
    • Must have worked on complex, multi-core SoC's with extensive interconnects and a large range of peripherals.
    • Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must.
    • Must have strong track record of managing RTL design through several successful tape-outs.
    • Familiarly with system design, Software concepts and SoC micro-architecture and/or design.
    • Proficiency in C/C++, and scripting languages such as Python.
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