- Visa sponsored for candidates with 5+ years of relevant expertise
- Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage.
- Experience in CXL / DDR / MIPI / PCIe Protocol
- Understanding of BIST would be an added advantage.
- Familiarity with HDL's such as Verilog and scripting languages such as shell/Perl/Python highly desirable
- Good communication skills, debug and problem solving skills.
- Be a technical contributor in the Verification Tasks
- Work closely with team members to deliver quality products.
- Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs
- Works in a project and team oriented environment
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Verification Engineer
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Engr Staff, Design tl
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onsemi IndiaA staff analog design engineer is expected to quickly take a analog design block through all phases of the design process, including design, simulation, and supervision of the layout/verification processes and evaluation/debug of silicon samples.A staff Analog IC Design Engineer, ...
Digital Verification Engineer - india, India - Vhunt4U
Description
Job Description :
Expertise in the verification of IP or SOC cores.
System Verilog/Verilog coding of test benches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM.
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