- Ideal candidate will have 5 to 10 years of experience in DFT for IP or SOC designs
- Must be strong in digital logic design, DFT concepts & strong analytical ability
- Proficient in synthesis with DFT, Scan insertion, ATPG, MBIST & JTAG
- Expert in design and Implementation of DFT techniques like Boundary Scan, Memory BIST, Scan Insertion & ATPG at a block and toplevel in advanced technology nodes
- Handson experience with industry Standard tools like Cadence, Synopsys or Mentor
- Exposure to STA tool, timing closure & ECO implementation for DFT modes is a great plus
- Prior experience with postsilicon debug is an added advantage.
- Expertise in scripting languages such as Perl, TCL or shell
- Strong problem solving & debugging skills
- Good communication skills
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Principal Engineer
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Lead Engineer
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NXP Semiconductors Noida, India Full timeJob Opportunity: Seeking highly motivated, energetic, team-oriented Individual Contributorwilling to go deeper into logic design and take the challenge ofdeveloping Complex state of the art IPs using the latest advanced Design flow methodologies and efficient techniques. · The pe ...
DFT Lead - Delhi, India - MY Search
Description
Our client provides end to end semiconductor design services covering digital, analog, system design & embedded software. They are poised to be the fastest-growing semiconductor services company.They are looking for DFT Lead to be based at Bangalore and Noida with the following :
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