Lead Full chip Soc Sign off - Bengaluru

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify and test electronic systems. · ...

+Job summary · As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. · +IR Signoff CPU/high performance cores · Signal EM & P ...

· A leading technology innovator seeks a Hardware Engineer to plan, design, optimize, verify and test electronic systems that launch cutting-edge products. · The ideal candidate will have experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level. · Famil ...

The focus of this role is to build execute and sign off on the EMIR closure for the IP/Full chip SOC THE PERSON: · The candidate should have a passion for complex processor architecture digital design and verification in general. · ...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD our mission is to build great products that accelerate next-generation computing experiences from AI and data centers to PCs gaming and embedded systems. · The Role The focus of this role is to build execute and sign off on the EMIR cl ...

Job Description · The candidate to have a passion for complex processor architecture, digital design, and verification in general. The candidate should be team player who has excellent communication skills and experience collaborating with other engineers located in different sit ...

+Job summary · Sandiskunderstands how people and businesses consume data... We are committed to an inclusive environment where every individual can thrive through a sense of belonging... · EMIR closure at Tile /Partition/Subsytem/SOC level on a particular node · ...

Sandisk is looking for a Technologist/Lead Full chip Soc Sign-off to join their team in Bengaluru. The candidate should have experience with complex processor architecture, digital design, and verification. · EMIR closure at Tile /Partition/Subsytem/SOC level on a particular node ...

Job Description: EMIR Engineer (Electromigration & IR Drop) – VLSI · Role Overview · The EMIR Engineer is responsible for analyzing and ensuring the reliability of integrated circuits by performing Electromigration (EM), IR Drop, and Power Integrity analysis during physical desig ...

The EMIR Engineer is responsible for analyzing and ensuring the reliability of integrated circuits by performing Electromigration (EM), IR Drop, and Power Integrity analysis during physical design and sign-off stages. · Bachelor's or Master's degree in Electrical Engineering, Ele ...

Location: Bengaluru, India Experience: 10–15 years Industry: Semiconductors | AI | Networking | ASIC Design · Role Overview · As the Physical Design EM/IR/ESD Lead you will be the ultimate guardian of our · silicon reliability and power integrity. In the high-stakes world of AI S ...

Static Timing Analysis (STA) Engineer · Job Summary · The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing ...

Strong handson experience with EDA tools like Cadence Innovus Synopsys ICC2 or Mentor Olympus. · ...

We are looking for a Senior / Lead Physical Design Engineer who will own block-to-chip implementation and sign-off, driving designs from netlist handoff to GDSII.This role is intended for engineers who have successfully closed multiple tape-outs, can independently resolve complex ...

· • PNR Leads Required with Shorter Notice period to lead a Team for a Long-Term Project. · • Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc. · • Experience in PnR tools like ICC/Innovus with regards to physical convergence must. · • Understan ...

Requirement Gathering. · Introduce existing product solutions to the client, gather clients expectation. · Assist in mapping client expectation to the existing functionalities available in product. · Prepare customization inputs required to meet client expectation. · Requirement ...

We are seeking an experienced Contract SAP Project Manager to lead and coordinate our ongoing SAP implementation, including critical integrations with CRM (Zoho), Dealer Loyalty App, and company websites. · ...

We are looking for an experienced · Physical Design Lead Engineer · to drive end-to-end ASIC/SoC physical implementation from RTL to GDSII. · This leadership role requires deep expertise in advanced node physical design, strong sign-off knowledge, and the ability to mentor teams ...

We are a fast-growing semiconductor startup building next-generation ASIC and SoC solutions. We are looking for a Senior / Lead Verification Engineer to own and drive functional verification strategy and execution across complex IPs, subsystems, and full-chip SoCs. · ...

We are looking for an experienced IO Layout Engineer to join our team in Bangalore. · ...