Fullchip Floorplan Expert - Bengaluru, Karnataka, India - INTEL

INTEL

Verified Company

Bengaluru, Karnataka, India

1 week ago

Posted by:

Deepika Kaur

beBee Recuiter

Description

Responsibilities include but not limited to:

Top-down SoC Floorplan activities like best IP placement for latency/area in collaboration with architects, partitioning, PG grid creation, pin-cutting, bump-planning by working with package/platform.

Estimate die-area and define optimal physical dimensions for SoC by including product costs like die-per-reticle, right technology selection/metal stack and reuse from different product family.

Drive execution, and supervise progress of smaller blocks or sub-systems influencing their physical placement, shape, and channel planning to help them achieve best area and convergence schedule.

Plan short and long-term work schedule, understanding dependencies between different domains like top, block place and route.

Collaborate with other stake holders like the clock design to deliver the physical block level floorplans for APR and with the power delivery team on tradeoffs for metal allocation for signal and power.

Help drive methodologies, tools and best known methods to streamline Floorplan Physical Design work to achieve best-in-class on schedule delivery.

Qualifications:

Bachelor or Masters' degree in Electrical/Electronics/Computer Engineering with 7+ years of relevant experience.
Good Knowledge with all aspects of ASIC integration including Floorplanning, Clock and Power distribution, Global signal planning, I/O planning and Macro placement.
Familiar with hierarchical design approach, topdown design, handling MIB (multiple instantiation blocks), routing and physical convergence.
Deep knowledge of SoC Floorplan requirements like multiple voltage and clock domains, Level Shifters, thermal management, DietoDie interconnects, and package interactions.
Expertise with Floorplanning tools
ICC2/FC, Place and Rout flows, and Physical Design Verification Flows is required.
Experience with large subsystem designs (20M gates) with frequencies in excess of 2GHz and also on lower process nodes like TSMC N5 or below etc.
Good automation skills/focus with coding familiarity in tcl/perl/python GPU Dataflow understanding and familiarity is an added advantage.

Inside this Business Group:

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products.

From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations.

DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams.

As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

Working Model:

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

In certain circumstances the work model may change to accommodate business needs.
JobType

Hybrid