Sta, Synthesis - Bengaluru, India - Wafer Space
Description
_Desired Skills and Experience-_
- Detailed knowledge of EDA tools and flows, Tempus/Primetime experience is a must
- Wellversed with the timing closure (STA), timing closure methodologies
- Pre/Postlayout constraint development to timing closure
- Handshake with the design team and develop functional/DFT constraints
- IP level constraint integration
- Multivoltage/Switching aware corner definitions
- RC/C model selection understanding
- Abstraction expertise like Hyperscale/ILM/ETM
- RC Balancing and scaling analysis of full chip clock
- RC Balancing and scaling analysis of critical data paths
- Good automation skills in PERL, TCL, and EDA toolspecific scripting
