Senior DFT Engineer - Bangalore Division - Eteros Technologies

We are currently seeking a skilled DFT Engineer to join our team. · ...

We are looking for a DFT Engineer to work with cross‑functional teams on implementing and verifying advanced test features in complex IPs, subsystems, and SoCs. · Key Responsibilities: · • Implement DFT features including scan insertion, ATPG, memory BIST, IO BIST, and test acces ...

The Design for Testability (DFT) engineering for a leading Semiconductor company involves implementing various DFT techniques and conducting DFT simulations to ensure comprehensive test coverage. · ...

About the job · DFT Engineer · Location: Bangalore · Notice Period: 30 days · Job Description: · We are looking for a skilled DFT Engineer with 3+ years of experience in ASIC design and verification with a strong focus on Design-for-Test methodologies. You will be responsible for ...

DFT Engineer Role for ASIC design teams in Bangalore and Chennai. · ...

DFT engineer with 10+ yrs experience in SoC DfT implementation and verification of scan architectures. · ...

About the Role · As a DFT Engineer, you will be a key player in ensuring the reliability and manufacturability of our next-generation silicon. In 2026, the complexity of AI-driven chips requires advanced testability solutions. You will own the DFT flow from architecture to sign-o ...

DFT Engineer · Location: Bangalore · Notice Period: 30 days · Job Description: · We are looking for a skilled DFT Engineer with 3–5 years of experience in ASIC design and verification with a strong focus on Design-for-Test methodologies. You will be responsible for implementing a ...

DFT Engineer with 5+ years of experience in Chip level DFT and Post Silicon debug/analysis. Proficient in Python, PERL/Shell script and SDC constructs. · ...

We are looking for a DFT Engineer to join our dynamic team in Hyderabad and Banglaore. The successful candidate will have experience with industry-standard tools and flows for DFT architecture and methodologies for ASIC/SoC designs. · Develop and implement DFT architecture and me ...

DFT engineer to develop methodologies and implement DFT for pre/post-silicon DFT flow contributing to SOC/Automotive/RISC-V product test quality. · ...

Architect implement and validate innovative DFT techniques on ARM SoCs inserting DFT logic into SoC style designs at the RTL level and at the Synthesis gate level validating all features and generating ATE targeted test patterns to be run on silicon. · ...

Manager, DFT · Responsibilities: · Responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug and diagnostics needs of the memories in design. · Work closely with the design, design-verification, and backend teams to enable the ...

DFT Engineers responsible for delivering complex IPs using latest advance Design for Test skills and Tools . · ...

We are looking for a DFT Engineer to join our team. The successful candidate will have experience in designing and implementing DFT techniques on ARM SoCs. · ...

NVIDIA is an equal opportunity employer. · We are looking for a DFT engineer to work on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. · ...

Designing and implementing DFT techniques for complex SOCs to improve testability. · ...

Exciting Opportunity for · DFT Engineers · Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. · Role Description · Should have good post silicon DFT bring up and deb ...

DFT Engineer with 5+ years of experience in Chip level DFT and Post Silicon debug / analysis. · ...

Position: DFT Engineer · Experience: 4+ Years · Employment Type: Full-Time Hiring · Client: Neurealm · Work Location: Bangalore / Cochin / Pune / Chennai · Role Overview · We are seeking an experienced DFT (Design for Test) Engineer with strong expertise in scan insertion, ATPG g ...

We are looking for a skilled Design for Test (DFT) Lead Engineer with experience in ASIC/SoC development to drive technical ownership of DFT implementation and mentoring junior engineers within fast-paced semiconductor projects. ...