- Developand execute verification plans for complex RTLdesigns.
- Perform functional and performanceverification of design blocks.
- Collaborate withcrossfunctional teams to ensure successful IP componentintegration.
- Contribute to enhancingverification methodologies and bestpractices.
- Experiencewith formal verification tools andmethodologies.
- Familiarity with scriptinglanguages (e.g. Python Perl) for automationtasks.
- Knowledge of industrystandard protocolsand interfaces (e.g. PCIe AXIAHB).
- Opportunitiesfor professional growth and careeradvancement.
- Vibrant and inclusive work culturethat values collaboration andinnovation.
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Design Verification Engineer
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Group Leader Propulsion Controls Software
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Hiring For Python Developer InternWeb
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RazormetTechnologies Sany, IndiaWe are looking for a Python Web Developerresponsible for managing the interchange of data between the serverand the users. Your primary focus will be the development of allserverside logic ensuring high performance and responsiveness torequests from the frontend.You will also ber ...
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Python Developer Fresher New Batch-
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GLOBALTALEX PRIVATE LIMITED Sany, IndiaResponsibilities: · Build NAND product/Testchip test development validationcharacterization & qualification · Partnerwith Process Integration yield engineering to improve overall dieyield and meet the critical milestones planned for thetestchip · NAND product test mode definition ...
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Azure Tech Lead
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Design verification Engineer - Sany, India - ARF
8 hours ago
Description
: RTLDesign VerificationEngineer
:5 Years
:Bangalore/Bhubaneswar
::
:
Bachelorsor masters degree in electrical engineering/Electronics &Communication Engineering or relatedfield.
::
Minimumof 5 years of experience in RTL designverification.Proficiency in Verilog/ SystemVerilog and experience with industrystandard verificationmethodologies (OVM/UVM).Strong understandingof ASIC design flow and verificationtechniques.Excellent problemsolving anddebuggingskills.
:
:
If youreready to take your career to the next level and contribute togroundbreaking projects we want to hear fromyou
/
: Pleasename the file in the following format: YourFull
.
design,verilog,rtldesign,communication,universal verification methodology(uvm),semiconductor device