Asic Digital Design Engg Ii - Bengaluru, India - Synopsys

Synopsys

Verified Company

Bengaluru, India

1 week ago

Posted by:

Deepika Kaur

beBee Recuiter

Description

45613BR

INDIA
Bangalore, INDIA
Pune

Job Description and Requirements

At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.ASIC Digital Design Engineer II**-
Key Qualifications

BSEE or MSEE plus a minimum of 2 years of digital design and verification experience in the industry
Good experience in writing blocklevel testcases including constrained directed random tests
Must be familiar with Verilog and VCS. Good knowledge of backend synthesis tools DC/PT is required
Must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows
Scripting experience in Shell, Perl, Python and TCL is a plus
Good theoretical and practical understanding of digital signal processing and data recovery circuits is required
Good communication skills for interacting between different design groups and customer support teams are required
Must be selfmotivated, proactive, and able to balance good design quality while meeting tight deadlines
Resolves issues in creative ways and exercises independent judgment in selecting methods and techniques to obtain solutions
May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise
Must exhibit ability to produce good results as an individual and team contributor

Preferred Experience

RTL coding, modeling of analog blocks, and writing complex systemlevel testbenches in Verilog
Defining synthesis design constraints and resolving STA issues as well as gatelevel simulation failures
Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools
Enhancing and maintaining existing SERDES PHY IPs supporting multiple protocols
Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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