Lead RTL Engineer - Bangalore Urban - Tessolve

    Tessolve
    Tessolve Bangalore Urban

    2 days ago

    Engineering / Architecture
    Description

    Job Description:

    • Design and implement digital circuits at the RTL level using Verilog/SystemVerilog or VHDL.
    • Translate architectural specifications into synthesizable RTL code.
    • Perform RTL simulations and debug logic issues.
    • Collaborate with verification engineers to develop and review test plans and coverage.
    • Support synthesis, timing analysis, and logic equivalence checks (LEC).
    • Interface with physical design and DFT teams to ensure design feasibility and testability.
    • Optimize designs for performance, area, and power.
    • Participate in design and code reviews.

    Required Skills and Qualifications:

    • Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
    • Strong understanding of digital logic design principles.
    • Proficient in RTL design using Verilog/SystemVerilog or VHDL.
    • Familiarity with ASIC or FPGA design flows.
    • Experience with simulation tools (e.g., ModelSim, VCS) and debugging techniques.
    • Basic understanding of synthesis, static timing analysis (STA), and formal verification.
    • Strong problem-solving and communication skills.
    • Ability to work collaboratively in a team environment.

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