- As a Verification engineer, should have handson experience related to the block level, subsystem level, and chip toplevel verification.
- Development and working with objectoriented verification languages (System Verilog, UVM)
- Have a background in Mixed Signal devices.
- Able to handle multiple blocks (good at time management).
- Good at debugging design and environmentrelated issues.
- Should work closely with the designers to understand the design changes and implement the same in Verification.
- Should be good with scripting languages.
- Should be good at Digital basics.
- Develop environment and tests for blocklevel verification and extend the same to block and chip toplevel verification.
- Good understanding of RAL, Code coverage, and functional coverage and implementing the same.
- Scripting using Perl, Python, and Shell.
- Simulations using gatelevel netlist at various PVT corners.
- Generation of vcd files for power analysis.
- Good understanding of DFT concepts and running ATPG simulations
- Working with analog and architecture teams to handle the integration of netlist and models into the test environment.
- Usage of FPGAbased validation platform in the lab.
- Handling of bringup and characterization lab activities.
- Support customer queries and their debug activities.
- Ability to work and communicate effectively in a team and to be able to multitask effectively in a fastpaced work environment.
- A technologyrelated bachelor's degree or higher with 812 years of related experience in verification roles.
- Experience in mixed signal devices.
- Fulltime role with work from the office located in Bangalore.
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Verification Engineer - Bangalore, India - Talent Scout Management Solution
1 week ago
Description
Verification Engineer ASICJob Overview Duties include :
Essential Functions :
Requirements :