- The candidate is expected to develop in depth understanding of chip architecture and define/ develop performance verification scenarios to test design/ architecture and report bottlenecks/ optimization opportunities. The test cases should cover system scenarios/ benchmarks which stress target path/ feature as well as subsystem analysis.
- The reference metrics to qualify the results needs to be synthesized based on references from system architecture team, software team, IP team, industry standards or defined based on abstract use case descriptions available as part of design requirements.
- Establish performance correlation with different levels of abstraction – TLM model, RTL and emulation. Also, work with silicon validation to support/ extend the correlation to final silicon and focus analysis based on customer feedback/ quality incident/ special use case requirements.
- Designing / developing performance tests (including performance benchmarks) with deep understanding of Use Case and hardware systems
- Arrive at actionable list of improvements in design centred around ARM/Network on Chip/Cache coherent Interconnects/DDR Controllers/Memory Subsystems
- Working with cross domains - IP owners, Systems and Core design teams to achieve performance verification objectives and / or close performance verification loop with SW deliverables
- Analysing big data space and correlate across metrics to identify design/ architecture issues. This usually involves building on more targeted scenarios with the goal to generate adequate data to understand design architecture behaviour under different traffic profiles.
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Design Verification Engineer
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Principal Verification Engineer - Noida, India - NXP Semiconductors
Description
Today's complex SOCs have demanding performance goals. Meeting these goals is critical for success of these parts. The performance verification team is responsible to qualify that the design architecture and implementation meets these goals with detailed metrics analysis and cross correlation across model, RTL, emulation.
Some of the challenging responsibilities include:
Job Qualifications:
Experienced SoC Verif Engineer with hands-on exposure of at-least 2 of the following skill sets:
1. Working experience of SoC Verif of Multi core SoCs on UVM TBs.
2. Working experience of ARM based Debug sub-system verification.
3. Working experience of Safety / Security Verification of SoCs.
4. Working experience of Low Power Verification .
5. Working experience of NoC Verification.
6. Working experience of Clock/Reset Archi of SoC.
7. Working experience of generating Functional Tester Patterns for ATE.
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