- Subsystem Place and Route, Physical verification, Timing closure.
- Resolve congestion, timing, power, runtime related issues in Physical design
- Experiment and execute techniques to improve PPAS.
- Coordination with chip level build activities, fully resolves schedule dependencies from his/her ownership
- Understand dependencies of his/her deliveries in chip level scope, and highlight gating issues on time, every time; deliver on time to void dependencies
- A minimum of 5+ years of exclusive partition physical design experience
- Fully aware of atleast one EDA tool to do Place and Route.
- Is very good with at least one programming language like TCL/PERL
- Works on ambitious, results-oriented schedule
- Excellent at debug, a quick learner & has applied analytical skills on job
- Bachelors of Engineering/Master of Technology in E&C/Electrical/Computer Science.
- Strong verbal communication skills
- Analog/MS/RF layout/design experience
- Multi-mode constraint design experience
- Low power checks, Formal verification experience
- ESD - Need, Implement, Check mechanism - exposure to
- Power integrity/Signal integrity experience
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Senior Engineer - bangalore, India - Micron
Description
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
JR49376 Senior Engineer - ASIC Physical DesignResponsibilities
Requirements
Preferred Skills: