- Responsible for independent planning and execution of all aspects of physical design
- Must have participated in all stages of the design (floor planning, placement, CTS, routing,
- Well versed with the timing closure (STA), timing closure methodologies.
- Good Understanding of DRC, LVS,ERC and PERC rule files for lower tech node layout
- Experience in lower tech nodes (7nm).
- Good automation skills in PERL, TCL and EDA tool-specific scripting.
- Able to take complete ownership for Block/sub-system for complete execution cycle.
- Out of box thinking to meet tighter PPA requirements.
- Any implementation experience within the field of CPU/GPU IP designs
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Senior Physical Design Engineer - bangalore, India - ACL Digital
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Description
Deep understanding of the concepts related to synthesis, placement & route, CTS, timingconvergence, IR/EM checks and signoff DRC/LVS closure.
Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM.
Nice To Have - Skills and Experience: