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    Sr. Principal Design Engineer - Bengaluru, India - L&T Semiconductor Technologies

    L&T Semiconductor Technologies
    L&T Semiconductor Technologies Bengaluru, India

    6 days ago

    Default job background
    Engineering / Architecture
    Description

    Role - Sr. Principal Design Engineer - DFT (Design-for-Testability)

    Stream - Customer Focused Product Development for Mobility, Industrial, Energy & Telecom

    Reporting To - Chief Development Officer / Global Head of Engineering

    Location -Bengaluru

    COMPANY DESCRIPTION

    L&T Semiconductor Technologies (LTSCT), a fully owned subsidiary of L&T, is the first major Indian Semiconductor product company a fabless company for designing & delivering Smart Devices for Global Customers. A company that provides Semiconductor Devices and Technology partnerships by helping customers realise energy efficient, high performance systems to benefit from data, electrification and software defined technology trends.

    Harnessing the engineering mastery of L&T, LTSCT is forging a path to a worldclass semiconductor ecosystem rooted in India. We aim to rewrite the rules of cutting-edge technology through relentless innovation to foster a vibrant culture of ingenuity, fuelling progress on every chip.

    We have a presence in four prominent geographies i.e. US, Europe, Japan and India, with offices in Austin, Munich, London, Tokyo, Bangalore and Chennai.

    JOB DESCRIPTION

    LTSCT's Chief Development Organization and Global Engineering team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for LTSCT's Automotive, Industrial, Energy and Telecom infra business lines. The team is challenged to produce industry leading solutions covering very cost sensitive, low power devices to highly integrated, high performance, multidomain devices compliant with the latest automotive and industrial safety and security standards.

    AREAS OF RESPONSIBILITY:

    Leading DFT implementation, integration and verification of System-on-Chip (SoC) from initial specification till tape out and production.

    Addressing test quality targets in DFT architecture and test pattern generation.

    Leading various aspects of Test architecture including Scan & ATPG, Memory BIST, Logic BIST, Analog/PHY test and post-silicon support.

    Work with different functions like front-end design, verification and physical design to ensure production quality silicon.

    Support post-silicon activities, working with test engineering and validation teams.

    • knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.
    • with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality.

    Qualification

    • Master/Bachelor's Degree in Electrical/Electronic Engineering.
    • Min. 15 years of experience in DFT domain with successful delivery of production quality chips. Should possess experiences in all aspects of DFT, including scan & ATPG, memory BIST, logic BIST, Analog test, and post-silicon support.
    • Good understanding of design flow from specification / micro-architecture definition to design and verification, timing analysis, and physical design.
    • Self-motivated. Excellent written and verbal communication skill.
    • Creative problem-solving skills, logic analysis skills, ability to logically break complex problems down to manageable components.
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