- Perform comprehensive verification of FPGA designs based on functional requirements using simulation tools.
- Create robust test benches utilizing System Verilog (SV) and Universal Verification Methodology (UVM) for efficient verification.
- Develop thorough test cases and procedures to cover all functionalities and corner cases of the design.
- Troubleshoot test bench issues and analyze simulation results to identify and debug design bugs.
- Collaborate with FPGA Design Engineers to resolve design verification issues.
- Stay uptodate with the latest trends and advancements in FPGA verification methodologies.
- Minimum 6 years of experience in FPGA verification using simulation environments.
- Strong expertise in test bench creation, troubleshooting, and verification planning.
- Indepth knowledge of System Verilog (SV) and its constructs for verification purposes.
- Proficiency in Universal Verification Methodology (UVM) for modular and reusable test environments.
- Experience in developing comprehensive test cases and procedures.
- Excellent analytical skills with the ability to interpret simulation results and identify design flaws.
- Effective communication and collaboration skills to work seamlessly with design teams.
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FPGA Verification Engineer - bangalore, India - Excellence and Eminence LLP
Description
About the Role :
We are seeking a highly skilled FPGA Verification Engineer to join our team and play a crucial role in ensuring the functionality and performance of our client's FPGA designs.
This role is ideal for a candidate with extensive experience in verification methodologies and expertise in using industry-standard verification languages.
Responsibilities :
Requirements :