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    RTL Design Engineer - Bangalore, India - MySearch

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    MySearch Bangalore, India

    4 days ago

    Default job background
    permanent Engineering / Architecture
    Description
    Job Description

    Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)

    • Write design specifications for different functional blocks on a chip, Create microarchitecture diagrams of functional blocks, Design functional blocks using System Verilog RTL code, conduct Synthesis and place and route to meet timing / area goals
    • Contribute to Design Verification, Synthesis, Power Reduction, Timing Convergence & Floorplan efforts
    • Responsible for logic implementation of complex design block(s) using RTL coding techniques (Verilog)
    • Code Verilog RTL for high performance designs with supervision from manager and input from peers and architects in the engineering team
    • You handle Verilog RTL logic design and debug
    • Develop RTL for logic blocks and participate in Front End activities like Synthesis, Timing Closure & FPGA implementation
    • Contribute as a design engineer developing the nextgeneration of multicore processors
    • Specify, design, and synthesize RTL blocks, optimize and floorplan them
    • Work with verification engineers to ensure their accuracy
    )
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