- Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
- Design Verification experience verifying complex designs and leading projects from concept to verification closure.
- Strong handson UVM and System Verilog coding experience and functional verification environment development is required.
- Experience working on verifying any Serial IP or Interface protocols (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C)
- Formal verification and/or Emulation experience is desirable.
- AMBA protocol (AXI5, CHI, CXS) experience is a desirable.
- Familiarity with using 3rd party VIPs, Cadence preferred.
- Team player with strong communication skills, and ability to work independently on the verification of a portion of the design.
- Prior experience in IP development teams would be an added advantage.
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Design & Verification Engineer - System Verilog - pune, India - Digicomm
Description
Job Description :
BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
At least 3 Years of relevant Industry experience