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    SRAM Design Engineer - bangalore, India - MediaTek

    MediaTek
    MediaTek bangalore, India

    6 days ago

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    Description
    Job DescriptionSRAM DESIGN

    Team:
    End to end SRAM design for Mediatek's processors (CPU, GPU, AI) - SRAM Design, Layout, Qualification, Release, Silicon validation

    Qualification:
    Required Experience : 5 – 8 Years

    Degree :
    ME/M.Tech in Electronic Engineering


    R&R:
    Working with the SRAM team responsible for FCI design for xCPU systems from R2G.
    Collaborate with CPU/GPU/APU team to define design specifications.
    Optimize SRAM architecture/topologies for power, timing, area, and yield.
    Implement custom circuits for Single Port & Two Port SRAM Designs.
    Perform schematic capture, simulations/analysis, and margin verifications.
    Performing timing, power, and leakage measurements, as well as post-layout optimizations.
    Work closely with the layout team to optimize layout design.
    SRAM Design validations (EM/IR, Power On, Lockup, functional simulations etc.).
    Collaborate closely with the Front-End model team to develop System Verilog/TMAX/CTL/UPF models for SRAM design.
    Provide support for post-silicon efforts to enable productization and collaborating closely with the Post-silicon team for debugging when necessary.

    Preferred qualifications include proficiency in a scripting language (such as Python or Perl) and Hardware Description Language (Verilog, System Verilog).


    Tools :
    XA, AFS-Mega, HSPICE, NANOTIME, Virtuoso, Custom Compiler, XA-RA, Totem.

    RequirementSRAM DESIGN

    Team:
    End to end SRAM design for Mediatek's processors (CPU, GPU, AI) - SRAM Design, Layout, Qualification, Release, Silicon validation

    Qualification:
    Required Experience : 5 – 8 Years

    Degree :
    ME/M.Tech in Electronic Engineering


    R&R:
    Working with the SRAM team responsible for FCI design for xCPU systems from R2G.
    Collaborate with CPU/GPU/APU team to define design specifications.
    Optimize SRAM architecture/topologies for power, timing, area, and yield.
    Implement custom circuits for Single Port & Two Port SRAM Designs.
    Perform schematic capture, simulations/analysis, and margin verifications.
    Performing timing, power, and leakage measurements, as well as post-layout optimizations.
    Work closely with the layout team to optimize layout design.
    SRAM Design validations (EM/IR, Power On, Lockup, functional simulations etc.).
    Collaborate closely with the Front-End model team to develop System Verilog/TMAX/CTL/UPF models for SRAM design.
    Provide support for post-silicon efforts to enable productization and collaborating closely with the Post-silicon team for debugging when necessary.

    Preferred qualifications include proficiency in a scripting language (such as Python or Perl) and Hardware Description Language (Verilog, System Verilog).


    Tools :
    XA, AFS-Mega, HSPICE, NANOTIME, Virtuoso, Custom Compiler, XA-RA, Totem.
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