- Job Location: Bangalore
- Experience: 5yrs to 12yrs
- Senior Design & Verification Engineers (IP/SOC)
- In this role, you will be creating UVM testbenches for an SoC and IP, as well as tests, regressions, and functional coverage to achieve zero bug escapes.
- You will interface with the designers to develop the test plans, and from that develop testcases and coverage to thoroughly verify the RTL.
- Your regressions will grow to cover the full functionality of the design relative to the architectural simulator and will include corner case testing for the more challenging cases.
- Your test and coverage reviews will ensure key coverage.
- ESSENTIAL DUTIES AND RESPONSIBILITIES:
- Create UVM testbenches, tests, and constraints to ensure design correctness
- Design, develop, and maintain modular and reusable UVM testbenches for blocks
- Collaborate with colleagues to develop test plans
- Create randomized tests, adding constraints and directed tests to fully cover functionality
- Confirm test completeness through code and functional coverage
- Review testbenches, tests, and coverage with designers, architects, and SW engineers
- Integrate tests and coverage within full environment
- Write C based BareMetal code for SoC level verification
- Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.
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Senior ASIC verification Engineers - Bengaluru, India - Synopsys Inc
Description
We are looking for experienced IP/SOC Verification Engineers in Bangalore for the following role and with the given background/skill sets. Does this sound like a good role for you?
Please share your updated CV with or refer those who would like to explore this opportunity.