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    Sr Design Manager Digital IP - Bengaluru, India - L&T Semiconductor Technologies

    L&T Semiconductor Technologies
    L&T Semiconductor Technologies Bengaluru, India

    5 days ago

    Default job background
    Engineering / Architecture
    Description
    Role - Sr Design Manager - Digital IP

    Stream - R&D

    Reporting To - Chief Development Officer / Global Head of Engineering

    Location -Bengaluru


    COMPANY DESCRIPTION:


    L&T Semiconductor Technologies (LTSCT), a fully owned subsidiary of L&T, is the first major Indian Semiconductor product company - a fabless company for designing & delivering Smart Devices for Global Customers.

    A company that provides Semiconductor Devices and Technology partnerships by helping customers realise energy efficient, high-performance systems to benefit from data, electrification and software defined technology trends.

    Harnessing the engineering mastery of L&T, LTSCT is forging a path to a world-class semiconductor ecosystem rooted in India.

    We aim to rewrite the rules of cutting-edge technology through relentless innovation to foster a vibrant culture of ingenuity, fuelling progress on every chip.

    We have a presence in four prominent geographies i.e. US, Europe, Japan and India, with offices in Austin, Munich, London, Tokyo, Bangalore and Chennai.


    JOB DESCRIPTION:


    LTSCT's Chief Development Organization and Global Engineering team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for LTSCT's Automotive, Industrial, Energy and Telecom infra business lines.

    The team is challenged to produce industry leading solutions covering very cost sensitive, low power devices to highly integrated, high performance, multidomain devices compliant with the latest automotive and industrial safety and security standards.


    AREAS OF RESPONSIBILITY:

    • Leading design, Micro-Architecture and Integration of IP.
    • Drive and implement best IP design methodology/practices.
    • Responsible for RTL, synthesis, timing constraints, CDC, RDC and work with different functions like verification, DFT etc. to get to a production ready IP.
    • Responsible for the presilicon verification of AI/ML processing blocks, RISCV processors or similar digital IPs.
    • Responsible for defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications)
    • Documenting the IP design and microarchitecture for usage by other functions
    • Provide design support for any silicon related debugs of chips in postsilicon phase.
    • Interface to HW, FW, and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP or subsystem.
    • Responsible for executing verification plan according to the product specification and verification requirements defined by product architects and deliver zero defect IPs.
    • Responsible for architecting, developing, debugging, and running UVM based verification environment for RTL simulation.
    • Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage.

    QUALIFICATIONS:

    • Degree in Electrical Engineering or Computer Science, with minimum 15 years of experience on IP/Sub-System Verification. Masters degree in the area of computer or electrical engineering from a reputed university will be an added advantage
    • Experience in all aspects of RTL design flow from Specification/Microarchitecture definition to design and verification, Timing Analysis, DFT and Implementation.
    • Proficient in digital design and handson experience with Verilog/System Verilog RTL coding
    • Firm understanding and handson experience on Chip Assembly, IP Integration, RTL signoff tools and CDC/RDC/Lint/Synthesis.
    • Familiarity with Computer architecture: knowledge of microprocessors, bus protocols preferred (AXI/ACE/APB/ATB). Knowledge on CPU architecture, coherency protocols, Virtualization, Coresight and peripherals like PCIe, USB, DDRs is highly desirable.
    • Strong domain knowledge of Clocking, Reset, System modes, Power management, debug, interconnect, safety, security and other architectures Knowhow of Serial Interfaces, Multimedia, External Bus Interfaces, ISO26262 based functional safety relevant microprocessor architectures is preferred.
    • Experience leading design teams; selfmotivated to drive issues to closure; ability to work with cross functional teams on issues resolution.
    • Creative problemsolving skills, logic analysis skills, ability to logically break complex problems down to manageable components.
    • Excellent written and verbal communication skill.
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