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    - Physical Design/Place and Route/Synthesis/Power planning - Hyderabad, India - Silicon Labs

    Silicon Labs
    Silicon Labs Hyderabad, India

    14 hours ago

    Default job background
    Full time
    Description

    We are Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.

    What we're looking for:

    It is if you are a highly motivated, self-driven, talented Engineer with demonstrated knowledge of the IC design flow, all the way from initial idea to implementation and manufacturing.

    Engineers inquiring about this position should be familiar with digital implementation tools with focus on back-end implementation tasks like, floor-planning, clock-tree-synthesis, power-planning, timing and routing optimization as well as physical ECO implementation.
    High level of scripting in TCL, perl and python is required to maintain and develop implementation flows.

    Successful candidates will have excellent written and oral communication skills and will be comfortable explaining technical concepts to a wide range of audiences, including senior engineering leaders.

    The candidate will be a technical contributor as part of a digital engineering team implementing highly integrated mixed signal SoC's for IoT products performing back-end implementation using deep sub micron technology.

  • Block and chip level floorplanning, pre-wire and timing-optimization tasks
  • Data preparation of IP like analog and RF macros.
  • Detailed place and route for both block macros and chip level, including clock-tree-synthesis, power routing, timing driven placement and routing, signal integrity analysis, and design for yield techniques
  • Generation of detailed parasitic information
  • Static and Dynamic rail analysis
  • Signoff Static Timing Analysis
  • Physical verification, including LVS and DRC
  • Maintenance of PnR flows
  • Development of new flow features and tool evaluations

    • Skills you'll need:

  • Strong knowledge of engineering fundamentals
  • Knowledge of System-On-Chip or ASIC design, and understanding of SoC or ASIC tools/flows
    Advanced design implementation skills: synthesis, floorplanning, clock tree synthesis, power routing and analysis, timing driven place and route, signal integrity analysis, parasitic generation, static timing analysis, physical verification
  • Advanced knowledge of low power flows, including voltage/power domains, power shutoff, retention.
  • Advanced knowledge of CMOS fabrication processes
  • Understanding of design for test techniques, including scan insertion, ATPG, Memory BIST, JTAG
  • Knowledge of scripting/language (perl, shell, tcl, python)
  • Familiarity with Quality systems and procedures
  • Excellent written and verbal communication skills

    • Education:

  • MS in Electrical Engineering, or equivalent

    • Benefits & Perks :

    Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

  • Equity Rewards (RSUs)
  • Employee Stock Purchase Plan (ESPP)
  • Insurance plans with Outpatient cover
  • National Pension Scheme (NPS)
  • Flexible work policy
  • Childcare support
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